There is a trend within the electronics industry towards the design and development of smaller electronic components. This trend has led to the fabrication of circuit boards having an increased component density. As the density of components on a given size circuit board has increased, it has become increasingly more difficult to successfully test the components themselves and the connections between them using the traditional bed-of-nails test technique.
In order to facilitate circuit board testing, a test technique known as Boundary-Scan has been developed. To accomplish Boundary-Scan testing, the architecture of one or more semiconductor devices on the board must be modified such that each device has one or more single-bit register cells (i.e., Boundary-Scan cells). Each Boundary-Scan cell within a Boundary-Scan architecture semiconductor device is coupled to an input/output pin of that device. Additionally, the Boundary-Scan cells within each device are coupled in a serial chain with each serial chain of Boundary-Scan cells in each of the other semiconductor devices on the board to form a single serial register chain. For purposes of discussion, a circuit board having Boundary-Scan architecture devices is itself said to have a Boundary-Scan architecture.
Actual Boundary-Scan testing is carried out by shifting a known stream of bits through the serial chain of Boundary-Scan cells in the semiconductor devices on a circuit board such that each bit is latched in a separate Boundary-Scan cell in the chain. If there are no faults (i.e., all of the Boundary-Scan architecture semiconductor devices are functioning properly, and all of the requisite interconnections between them are present), then the bit latched into each Boundary-Scan cell coupled to separate device output should appear at an input of another device coupled to that device output. The bit present at such an input will be captured so as to replace the bit previously latched into Boundary-Scan cell associated with that device input. By shifting out the stream of bits from the chain of Boundary-Scan cells after capturing, and comparing the stream to an expected set of values obtained under fault-free conditions, a faulty device or a faulty interconnection between devices will thus manifest itself. For a more complete description of the Boundary-Scan test technique, reference should be made to the document IEEE 1149.1 Test Access Port and Botmdary-Scan Architecture, published by the IEEE, New York, N. Y. (May, 1990), herein incorporated by reference.
Within an electronic system, such as a telephone switch, there is likely to be a large number of Boundary-Scan architecture circuit boards. One approach to testing such circuit boards via the Boundary-Scan test technique is to daisy-chain the boards together in a single large Boundary-Scan chain and then shift a stream of test values through the chain of circuit boards. The disadvantage of testing a plurality of Boundary-Scan architecture circuit boards in this fashion is the difficulty in determining which board is faulty. Another difficulty with testing a plurality of circuit boards in this fashion is that all of the boards which comprise the Boundary-Scan chain must be present. Otherwise if the chain is broken, the circuit boards cannot be tested.
Rather than test a group of circuit boards in a single chain, it is often more desirable to individually test each board in sequence by multiplexing test information and control signals to the boards. The disadvantage of performing Boundary-Scan testing in this manner is that the larger the number of circuit boards to be individually tested, the larger the number of control lines (i.e., bits) required to select the individual board of interest. The number of control lines n needed to select one of p separate boards is determined by the relationship p.ltoreq.2.sup.n. For example, to select one of thirty circuit boards would require five separate control lines. Providing a sufficient number of control lines to control a large number of circuit boards may present difficulties in terms of design and may increase the ultimate cost of testing. In addition, a separate control mechanism (in the form of a dedicated processor bus etc.) would be necessary to drive the parallel control lines.
Thus there is a need for a technique for controlling the testing of a plurality of systems (i.e. circuit boards) which is not subject to the aforementioned disadvantages.